Cphy rb3g2 rb4 rb8#693
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PR #693 — validate-patchPR: #693
Final Summary
Recommendation: Clean up commit messages (especially patch 08/13), remove WIP tags from subjects, address Bryan O'Donoghue's review feedback, and ensure all patches follow kernel commit message standards before merging or submitting upstream.
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PR #693 — checker-log-analyzerPR: #693
Detailed report: Full report
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PR #693 — validate-patchPR: #693
Final Summary
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PR #693 — checker-log-analyzerPR: #693
Detailed report: Full report
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Read PHY configuration from the device-tree bus-type and save it into the csiphy structure for later use. For C-PHY, skip clock line configuration, as there is none. Link: https://lore.kernel.org/linux-media/20260301-qcom-cphy-v4-1-e53316d2cc65@ixit.cz/ Signed-off-by: David Heidelberg <david@ixit.cz> Signed-off-by: Anusha Arun Nandi <aarunnan@qti.qualcomm.com>
…g C-PHY lanes So far, only D-PHY mode was supported, which uses even bits when enabling or masking lanes. For C-PHY configuration, the hardware instead requires using the odd bits. Since there can be unrecognized configuration allow returning failure. Link: https://lore.kernel.org/linux-media/20260301-qcom-cphy-v4-2-e53316d2cc65@ixit.cz/ Signed-off-by: David Heidelberg <david@ixit.cz> Signed-off-by: Anusha Arun Nandi <aarunnan@qti.qualcomm.com>
Inherit C-PHY information from CSIPHY, so we can configure CSID properly. CSI2_RX_CFG0_PHY_TYPE_SEL must be set to 1, when C-PHY mode is used. Link: https://lore.kernel.org/linux-media/20260301-qcom-cphy-v4-3-e53316d2cc65@ixit.cz/ Signed-off-by: David Heidelberg <david@ixit.cz> Signed-off-by: Anusha Arun Nandi <aarunnan@qti.qualcomm.com>
…on is available The lanes must not be initialized before the driver has access to the lane configuration, as it depends on whether D-PHY or C-PHY mode is in use. Move the lane initialization to a later stage where the configuration structures are available. Link: https://lore.kernel.org/linux-media/20260301-qcom-cphy-v4-4-e53316d2cc65@ixit.cz/ Signed-off-by: Petr Hodina <phodina@protonmail.com> Signed-off-by: David Heidelberg <david@ixit.cz> Signed-off-by: Anusha Arun Nandi <aarunnan@qti.qualcomm.com>
…HY init Add a PHY configuration sequence for the sdm845 which uses a Qualcomm Gen 2 version 1.1 CSI-2 PHY. The PHY can be configured as two phase or three phase in C-PHY or D-PHY mode. This configuration supports three-phase C-PHY mode. Link: https://lore.kernel.org/linux-media/20260301-qcom-cphy-v4-5-e53316d2cc65@ixit.cz/ Signed-off-by: Casey Connolly <casey.connolly@linaro.org> Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Co-developed-by: David Heidelberg <david@ixit.cz> Signed-off-by: David Heidelberg <david@ixit.cz> Signed-off-by: Anusha Arun Nandi <aarunnan@qti.qualcomm.com>
… CPHY init These values should improve C-PHY behaviour. Should match most recent Qualcomm code. Link: https://lore.kernel.org/linux-media/20260301-qcom-cphy-v4-6-e53316d2cc65@ixit.cz/ Signed-off-by: David Heidelberg <david@ixit.cz> Signed-off-by: Anusha Arun Nandi <aarunnan@qti.qualcomm.com>
…C-PHY init Add a PHY configuration sequence for the sm8250 which uses a Qualcomm Gen 2 version 1.2.1 CSI-2 PHY. The PHY can be configured as two phase or three phase in C-PHY or D-PHY mode. This configuration supports three-phase C-PHY mode. Link: https://lore.kernel.org/linux-media/20260301-qcom-cphy-v4-7-e53316d2cc65@ixit.cz/ Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: David Heidelberg <david@ixit.cz> Signed-off-by: Anusha Arun Nandi <aarunnan@qti.qualcomm.com>
…uration Catch when C-PHY configuration gets used on SoC with CAMSS missing C-PHY configuration lane registers. Hopefully this check will disappear as these lane regs gets populated. -- @BoD Proliferating special cases in switch statements on a per-SoC basis is verboten. Please find another way to do this, you already have a bool to indicate cphy in struct csid_phy_config {} so at some level CAMSS already has a bool to indicate what to do. Please make that logic accessible to logical consumers throughout, in this case the CPHY code. -- Link: https://lore.kernel.org/linux-media/20260301-qcom-cphy-v4-8-e53316d2cc65@ixit.cz/ Signed-off-by: David Heidelberg <david@ixit.cz> Signed-off-by: Anusha Arun Nandi <aarunnan@qti.qualcomm.com>
… frequency Ensure that the link frequency divider correctly accounts for C-PHY operation. The divider differs between D-PHY and C-PHY, as described in the MIPI CSI-2 specification. For more details, see: https://docs.kernel.org/driver-api/media/tx-rx.html#pixel-rate Link: https://lore.kernel.org/linux-media/20260301-qcom-cphy-v4-9-e53316d2cc65@ixit.cz/ Suggested-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: David Heidelberg <david@ixit.cz> Signed-off-by: Jigarkumar Zala <jzala@qti.qualcomm.com> Signed-off-by: Anusha Arun Nandi <aarunnan@qti.qualcomm.com>
Use these switch cases to add the sa8775p (CAMSS_8775P) 3-phase 1.5 Gsps settings, programming the appropriate common-control register 5/6/7 and reset-release values for C-PHY and D-PHY. Signed-off-by: Jigarkumar Zala <jzala@qti.qualcomm.com> Signed-off-by: Anusha Arun Nandi <aarunnan@qti.qualcomm.com>
Add the CSI2 RX PHY type select bitfield and program it from the configured PHY type so that the CSID RX path is told whether the incoming data is C-PHY or D-PHY. Signed-off-by: Jigarkumar Zala <jzala@qti.qualcomm.com> Signed-off-by: Anusha Arun Nandi <aarunnan@qti.qualcomm.com>
Add the lane_regs_sa8775p_3ph[] register table for the sa8775p Gen3 CSIPHY at 1.5 Gsps, and select it in csiphy_lanes_enable() for CAMSS_8775P when the endpoint is configured for C-PHY, falling back to the existing sa8775p D-PHY table otherwise. Signed-off-by: Jigarkumar Zala <jzala@qti.qualcomm.com> Signed-off-by: Anusha Arun Nandi <aarunnan@qti.qualcomm.com>
Share the C-PHY/D-PHY lane_regs selection for CAMSS_8300 so the sa8300 platform uses the same 3ph handling as CAMSS_8775P. Also drop CAMSS_8300 from the missing-C-PHY-table guard now that a C-PHY table is provided. Signed-off-by: Jigarkumar Zala <jzala@qti.qualcomm.com> Signed-off-by: Anusha Arun Nandi <aarunnan@qti.qualcomm.com>
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Signed-off-by: aarunnan <aarunnan@quicinc.com>
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Merge Check Failed: No CR Numbers Found Error: No Change Request numbers were found. Please add Change Request numbers to your pull request description in the format CRs-Fixed: 12345 or link GitHub issues that are associated with Change Requests. |
PR #693 — validate-patchPR: #693
Final Summary
Recommendation: Hold merge until upstream series is actually posted and lore links become accessible for diff verification. Once posted, re-validate that PR patches match the upstream submission exactly.
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PR #693 — checker-log-analyzerPR: #693
Detailed report: Full report
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7 participants
Added CPHY support of RB3G2, RB4 and RB8